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rev. prb preliminary technical data information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD9215 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2002 preliminary technical data 10-bit, 65/80/105 msps 3 v a/d converter functional block diagram sha vin+ vin reft refb drvdd a/d 3 7-stage 1 1/2-bit pipeline 14 clock pdwn mode clock duty cycle stablizer mode select drgnd or d9 (msb) d0 av d d correction logic output buffers 10 ref select a gnd 0.5v vref sense AD9215 features single 3 v supply operation (2.7 v to 3.6 v) snr = 58 dbc (to nyquist) sfdr = 78 dbc (to nyquist) low power: 75 mw at 65 msps differential input with 400 mhz bandwidth on-chip reference and sha dnl = 0.25 lsb flexible analog input: 1 v p-p to 2 v p-p range offset binary or two? complement data format clock duty cycle stabilizer applications ultrasound equipment if sampling in communications receivers battery-powered instruments hand-held scopemeters low-cost digital oscilloscopes product description the AD9215 is a fam ily of monolithic, single 3 v supply, 10-bit, 65 /80/105 msps analog-to-digital converters. this family features a high-performance sample- and-hold amplifier and voltage reference. the AD9215 uses a multistage differential pipelined architecture with output error co rrection logic to provide 10-bit accuracy at 105 msps data rates and guarantee no missing codes over the full operating tem perature range. the wide-bandwidth, truly differential sha allows for a variety of user-selectable input ranges and offsets including single-ended applications. it is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling s ingle-channel inputs at frequencies well beyond the nyquist rate. combined with power and cost savings over previously available analog-to-digital converters, the AD9215 is suitable for applica- tions in communications, imaging, and medical ultrasound. a single-ended clock input is used to control all internal conversion cycles. a duty cycle stabilizer compensates for wide variations in the clock duty cycle while maintaining excellent performance. th e digital output data is presented in straight binary or two? complement formats. an out-of-range signal indicates an over- flow condition, which can be used with the most significant bit to determine low or high overflow. f abricated on an advanced cmos process, the AD9215 is avail- able in both a 28-lead surface-mount plastic package and a 32-lead chip scale package, and is specified over the industrial temperature range (?0 c to +85 c). product highlights 1. the AD9215 operates from a single 3 v power supply, and features a separate digital output driver supply to accommo- date 2.5 v and 3.3 v logic families. 2. operating at 105 msps, the AD9215 consumes a low 120 mw. 3. the patented sha input maintains excellent performance for input frequencies up to 200 mhz, and can be configured for single-ended or differential operation. 4. the AD9215 is pin-compatible with the ad9235, a 12-bit, 20/40/65 msps a/d converter. this allows a simplified upgrade from 10 to 12 bits for systems up to 65 msps. 5. the clock duty cycle stabilizer maintains performance over a wide range of clock pulsewidths. 6. the or output bit indicates when the signal is beyond the selected input range.
rev. prb e2e AD9215especifications preliminary technical data dc specifications test AD9215bru/cp-65 AD9215bru/cp-80 AD9215bru/cp-105 parameter temp level min typ max min typ max min typ max unit resolution full vi 10 10 10 bits accuracy no missing codes guaranteed full vi 10 10 10 bits offset error full vi 0.30 1.20 0.30 1.20 0.30 1.20 % fsr gain error 1 full vi 0.30 2.00 0.30 2.00 0.30 2.00 % fsr differential nonlinearity (dnl) 2 full iv 0.25 1.00 0.25 1.00 0.25 1.00 lsb 25 ci lsb integral nonlinearity (inl) 2 full iv 1.90 1.90 1.90 lsb 25 ci 0.50 1.50 0.50 1.50 0.50 1.50 lsb temperature drift offset error full v 16 16 16 ppm/ c gain error 1 full v 150 150 150 ppm/ c reference voltage (1 v mode) full v 80 80 80 ppm/ c internal voltage reference output voltage error (1 v mode) full vi mv load regulation @ 1.0 ma full v mv output voltage error (0.5 v mode) full v mv load regulation @ 0.5 ma full v mv input referred noise vref = 0.5 v 25 cv lsb rms vref = 1.0 v 25 cv lsb rms analog input input span, vref = 0.5 v full iv 1 1 1 v p-p input span, vref = 1.0 v full iv 2 2 2 v p-p input capacitance 3 full v 5 5 5 pf reference input resistance full v 7 7 7 k power supplies supply voltages avdd full iv 2.7 3.0 3.6 2.7 3.0 3.6 2.7 3.0 3.6 v drvdd full iv 2.25 3.0 3.6 2.25 3.0 3.6 2.25 3.0 3.6 v supply current iavdd 2 full i 30 37 40 58 47 67 ma idrvdd 2 full i 7 9 11 ma psrr full v 0.01 0.01 0.01 % fsr power consumption dc input 4 full vi 75 90 120 mw sine wave input 2 full vi 95 115 110 145 145 200 mw standby power 5 full v 1.0 1.0 1.0 mw notes 1 gain error and gain temperature coefficient are based on the a/d converter only (with a fixed 1.0 v external reference). 2 measured at maximum clock rate, f in = 10.3 mhz, e0.5 dbfs, full-scale sine wave, with approximately tbd pf loading on each output bit. 3 input capacitance refers to the effective capacitance between one differential input pin and agnd. refer to figure 2 for the eq uivalent analog input structure. 4 measured with dc input at maximum clock rate. 5 standby power is measured with a dc input, the clock pin inactive (i.e., set to avdd or agnd). specifications subject to change without notice. (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, 1.0 v internal reference, t min to t max , unless otherwise noted.)
rev. prb e3e AD9215 preliminary technical data digital specifications test AD9215bru/cp-65 AD9215bru/cp-80 AD9215bru/cp-105 parameter temp level min typ max min typ max min typ max unit logic inputs high-level input voltage full iv 2.0 2.0 2.0 v low-level input voltage full iv 0.8 0.8 0.8 v high-level input current full iv e10 +10 e10 +10 e10 +10 a low-level input current full iv e10 +10 e10 +10 e10 +10 a input capacitance full v 2 2 2 pf logic outputs * drvdd = 3.3 v high-level output voltage full iv avdd e50 mv avdd e50 mv avdd e50 mv v low-level output voltage full iv 0.05 0.05 0.05 v note * output voltage levels measured with 5 pf load on each output. specifications subject to change without notice. switching specifications test AD9215bru/cp-65 AD9215bru/cp-80 AD9215bru/cp-105 parameter temp level min typ max min typ max min typ max unit clock input parameters max conversion rate full vi 65 80 105 msps min conversion rate full v 1 1 1 msps clock period full v 15.4 12.5 9.5 ns clock pulsewidth high 1 full v ns clock pulsewidth low 1 full v ns data output parameters output delay 2 (t od ) full v 2 4 6 2 4 6 2 4 6 ns pipeline delay (latency) full v 5 5 5 cycles aperture delay full v ns aperture uncertainty (jitter) full v ps rms wake-up time 3 full v ms out-of-range recovery time full v cycles notes 1 for the AD9215-65 model only, with duty cycle stabilizer enabled. dcs function not applicable for e20 and e40 models. 2 output delay is measured from clock 50% transition to data 50% transition, with 5 pf load on each output. 3 wake-up time is dependent on value of decoupling capacitors, typical values shown with 0.1 f and 10 f capacitors on reft and refb. specifications subject to change without notice. analog input ne3 ne2 ne1 n n+1 n+2 n+3 n+4 n+5 n+6 clock data out ne9 ne8 ne7 ne6 ne5 ne4 ne3 ne2 ne1 n t od = 6.0ns max 2.0ns min figure 1. timing diagram
rev. prb e4e AD9215especifications preliminary technical data (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, 1.0 v internal reference, t min to t max , unless otherwise noted.) ac specifications * test AD9215bru/cp-65 AD9215bru/cp-80 AD9215bru/cp-105 parameter temp level min typ max min typ max min typ max unit signal-to-noise ratio f input = 10.3 mhz 25 ci 57.0 59.5 56.5 59.0 56.5 59.0 dbc f input = 39 mhz full v dbc 25 ci 59.0 56.0 58.5 56.0 58.5 dbc f input = 51 mhz full iv dbc 25 ci 58.0 58.0 58.0 dbc f input = 70 mhz 25 cv 56.0 56.0 56.0 dbc f input = 100 mhz 25 cv dbc signal-to-noise ratio and distortion f input = 10.3 mhz 25 cv 56.5 59.0 56.0 58.5 56.0 58.5 dbc f input = 39 mhz full iv dbc 25 ci 58.5 55.5 58.0 55.0 58.0 dbc f input = 51 mhz full iv dbc 25 ci 57.5 57.5 57.5 dbc f input = 70 mhz full iv dbc 25 ci 55.5 55.5 55.5 dbc f input = 100 mhz 25 cv dbc effective number of bits f input = 10.3 mhz 25 ci 9.2 9.6 9.1 9.5 9.1 9.5 bits f input = 39 mhz full v bits 25 ci 9.5 9.0 9.4 9.0 9.4 bits f input = 51 mhz full v bits 25 ci 9.3 9.3 9.3 bits f input = 70 mhz full v bits 25 ci 9.0 9.0 9.0 bits f input = 100 mhz 25 cv bits worst harmonic (second or third) f input = 10.3 mhz 25 ci 68 75 68 75 68 75 dbc f input = 39 mhz 25 ci 65 75 65 75 65 75 dbc f input = 51 mhz 25 ci 73 73 dbc f input = 70 mhz 25 ci 70 70 70 dbc f input = 100 mhz 25 ci dbc spurious free dynamic range (excluding second and third) f input = 10.3 mhz 25 ci 70 78 70 78 70 78 dbc f input = 39 mhz full v dbc 25 ci 70 78 70 78 70 78 dbc f input = 51 mhz full v dbc 25 ci 75 75 75 dbc f input = 70 mhz full iv dbc 25 ci 72 72 72 dbc f input = 100 mhz 25 cv dbc note * snr/harmonics based on an analog input voltage of e0.5 dbfs referenced to a 1 v p-p full-scale input range. specifications subject to change without notice.
rev. prb ordering guide model temperature range package description package option AD9215bru-65 e40 c to +85 c 28-lead thin shrink small outline (tssop) ru-28 AD9215bru-80 e40 c to +85 c 28-lead thin shrink small outline (tssop) ru-28 AD9215bru-105 e40 c to +85 c 28-lead thin shrink small outline (tssop) ru-28 AD9215bcp-65 e40 c to +85 c 32-lead chip scale package (lfcsp) cp-32 AD9215bcp-80 e40 c to +85 c 32-lead chip scale package (lfcsp) cp-32 AD9215bcp-105 e40 c to +85 c 32-lead chip scale package (lfcsp) cp-32 AD9215-105pcb evaluation board 25 c AD9215bru-105 evaluation board (tssop) ru-28 AD9215-80pcb evaluation board 25 c AD9215bru-80 evaluation board (tssop) ru-28 (also covers AD9215-65) caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD9215 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device absolute maximum ratings 1 with respect pin name to min max unit electrical avdd agnd e0.3 +3.9 v drvdd drgnd e0.3 +3.9 v agnd drgnd e0.3 +0.3 v avdd drvdd e3.9 +3.9 v digital outputs drgnd e0.3 drvdd + 0.3 v clock, mode agnd e0.3 avdd + 0.3 v vina, vinb agnd e0.3 avdd + 0.3 v vref agnd e0.3 avdd + 0.3 v sense agnd e0.3 avdd + 0.3 v refb, reft agnd e0.3 avdd + 0.3 v pdwn agnd e0.3 avdd + 0.3 v environmental 2 operating temperature e40 +85 c junction temperature 150 c lead temperature (10 sec) 300 c storage temperature e65 +150 c explanation of test levels test level i. 100% production tested. ii. 100% production tested at 25 c and sample tested at specified temperatures. iii. sample tested only. iv. pa rameter is guaranteed by design and characterization testing. v. parameter is a typical value only. vi. 100% production tested at 25 c; guaranteed by design and characterization testing for industrial temperature range; 100% production tested at temperature extremes for mili- tary devices. ac specifications (avdd = 3 v, drvdd = 2.5 v, maximum sample rate, 2 v p-p differential input, 1.0 v internal reference, t min to t max , unless otherwise noted.) notes 1 absolute maximum ratings are limiting values to be applied individually, and beyond which the serviceability of the circuit may be impaired. functional operability is not necessarily implied. exposure to absolute maximum rating conditions for an extended period of time may affect device reliability. 2 typical thermal impedances (28-lead tssop); ja = 97.9 c/w; jc = 14 c/w. these measurements were taken on a 2-layer board in still air, in accordance with eia/jesd51-3. test AD9215bru/cp-65 AD9215bru/cp-80 AD9215bru/cp-105 parameter temp level min typ max min typ max min typ max unit two-tone intermodulation distortion (imd) f in1 = 29.3 mhz, f in2 = 30.3 mhz 25 cv 76 74 74 dbc f in1 = 70 mhz, f in2 = 71 mhz 25 cv 72 72 72 dbc f in1 = 140 mhz, f in2 = 141 mhz 25 cv 70 70 70 dbc AD9215 e5e preliminary technical data
rev. prb AD9215 e6e preliminary technical data pin function descriptions tssop lfcsp pin no. pin no. mnemonic description 12 1o r out-of-range indicator 22 2 mode data format and clock duty cycle stabilizer (dcs) mode selection 32 3 sense reference mode selection 42 4 vref voltage reference input/output 52 5 refb differential reference (negative) 62 6 reft differential reference (positive) 7, 12 27, 32 avdd analog power supply 8, 11 28, 31 agnd analog ground 92 9v in+ analog input pin (+) 10 30 vine analog input pin (e) 13 2 clock clock input pin 14 4 pdwn power-down function selection (active high) 17e22, 25e28 9e14, 17e20 d0 (lsb)ed9 (msb) data output bits 23 15 drgnd digital output ground 24 16 drvdd digital output driver supply. must be decoupled to drgnd with a minimum 0.1 f capacitor. recommended decoupling is 0.1 f in parallel with 10 f. 15-16 1, 3, 5e8 nc not internally connected av d d mode 20k 20k figure 2. equivalent analog input circuit av d d mode 20k figure 3. equivalent mode input circuit d11ed0, otr drvdd figure 4. equivalent digital output circuit 2.6k 2.6k av d d clock figure 5. equivalent digital input circuit pin configurations cp-32 pin 1 indicator top view 24 vref 23 sense 22 mode 21 or nc 1 clk 2 nc 3 32 avdd 20 d9 19 d8 18 d7 17 d6 ( lsb)d0 9 d1 10 d2 11 d3 12 d4 13 d5 14 dgnd 15 dvdd 16 pdwn 4 nc 5 nc 6 nc 7 nc 8 31 agnd 30 vine 29 vin+ 28 agnd 27 avdd 26 reft 25 refb AD9215 nc = no connect ru-28 1 2 3 4 5 6 7 8 9 10 11 12 13 14 otr mode sense vref refb reft av d d a gnd vin+ vine a gnd av d d clock pdwn d9 (msb) d8 d7 d6 drvdd drgnd d5 d4 d3 d2 d1 d0 (lsb) nc nc 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AD9215 top view (not to scale) nc = no connect
rev. prb AD9215 e7e preliminary technical data definitions of specifications integral nonlinearity (inl) inl refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each particular code to the true straight line. differential nonlinearity (dnl, no missing codes) an i deal a/d converter exhibits code transitions that are exactly 1 lsb apart. dnl is the deviation from this ideal value. guaranteed no missing codes to 12-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. offset error t he major carry transition should occur for an analog value 1/2 lsb below vin+ = vine. zero error is defined as the deviation of the actual transition from that point. gain error the first code transition should occur at an analog value 1/2 lsb above negative full scale. the last transition should occur at an analog value 1 1/2 lsb below the positive full scale. gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between first and last code transitions. temperature drift the temperature drift for zero error and gain error specifies the maximum change from the initial (25 c) value to the value at t min or t max . power supply rejection the specification shows the maximum change in full scale from the value with the supply at the minimum limit to the value with the supply at its maximum limit. aperture jitter aperture jitter is the variation in aperture delay for successive samples and can be manifested as noise on the input to the a/d converter. aperture delay aperture delay is a measure of the sample-and-h old amplifier (sha) performance and is measured from the rising edge of the clock input to when the input signal is held for conversion. signal-to-noise and distortion (s/n+d, sinad) ratio s/n+d is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the n yquist frequency, including harmonics but excluding dc. the value for s/n+d is expressed in decibels. effective number of bits (enob) for a sine wave, sinad can be expressed in terms of the num- ber of bits. using the following formula, n sinad = () ?. /. 176 602 it is possible to obtain a measure of performance expressed as n , the effective number of bits. thus, effective number of bits for a device for sine wave inputs at a given input frequency can be calculated directly from its measured sinad. total harmonic distortion (thd) thd is the ratio of the rms sum of the first six harmonic com- ponents to the rms value of the measured input signal and is expressed as a percentage or in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the measured input signal to the rms sum of all other spectral components below the nyquist frequency, excluding the first six harmonics and dc. the value for snr is expressed in decibels. spurious free dynamic range (sfdr) sfdr is the difference in db between the rms amplitude of the input signal and the peak spurious signal. clock pulsewidth and duty cycle pulsewidth high is the minimum amount of time that the clock pulse should be left in the logic 1 state to achieve rated per- formance: pulsewidth low is the minimum time the clock pulse should be left in the low state. at a given clock rate, these speci- fications define an acceptable clock duty cycle. minimum conversion rate t he clock rate at which the snr of the lowest analog signal fre- quency drops by no more than 3 db below the guaranteed limit. maximum conversion rate the clock rate at which parametric testing is performed. output propagation delay the delay between the clock logic threshold and the time when all bits are within valid logic levels. two-tone sfdr the ratio of the rms value of either input tone to the rms value of the peak spurious component. the peak spurious component m ay or may not be an imd product. may be rep orted in dbc (i.e., degrades as signal levels are lowered) or in dbfs (always related back to converter full scale). out-of-range recovery time out-of-range recovery time is the time it takes for the a/d con- verter to reacquire the analog input after a transient from 10% above positive full scale to 10% a bove negative full scale, or from 10% below negative full scale to 10% below positive full scale.
rev. prb AD9215 e8e preliminary technical data applying the AD9215 theory of operation the AD9215 ar chitecture consists of a front-end sample and hold amplifier (sha) followed by a pipelined switched capacitor a/d converter. the pipelined a/d converter is divided into two sections, consisting of seven 1.5-bit stages and a final 3-bit flash. each stage provides sufficient overlap to correct for flash errors in the preceding stages. the quantized outputs from each stage are combined into a final 10-bit result in the digital correction logic. the pipelined architecture permits the first stage to operate on a new input sample while the remaining stages operate on preceding sam ples. sampling occurs on the rising edge of the clock. each stage of the pipeline, excluding the last, consists of a low resolu tion flash a/d connected to a switched capacitor dac and interstage residue amplifier (mdac). the residue amplifier magnifies the difference between the reconstructed dac output and the flash input for the next stage in the pipeline. one bit of redundancy is used in each one of the stages to facilitate digital c orrection of flash errors. the last stage simply consists of a flash a/d. the input stage contains a differential sha that can be config- ured as ac- or dc-coupled in differential or single-ended modes. the output-s taging block aligns the data, ca rries out the error correction and passes the data to the output buffers. the output buffers are powered from a separate supply allowing adjustment of the output voltage swing. during power-down the output buffers go into a high-impedance state. analog input t he analog input to the AD9215 is a differential switched capacitor sha that has been designed for optimum performance while processing a differential input signal. the sha input can support a wide common-mode range and maintain excellent performance, as shown in figure 7. an input common-mode voltage of midsupply will minimize signal-dependent errors and provide optimum performance. referring to figure 6, the clock signal alternatively switches the sha between sample mode and hold mode. when the sha is switched into sample mode, the signal source must be capable of charging the sample capacitors and settling within one-half of a clock cycle. a small resistor in series with each input can help reduce the peak transient current required from the output stage of the driving source. also, a small shunt capacitor can be placed across the inputs to provide dynamic charging currents. this passive network will create a low-pass filter at the a/d?s input; therefore, the precise values are dependent upon the applica- tion. in if undersampling applications, any shunt capacitors should be removed. in combination with the driving source impedance they would limit the input bandwidth. for best dynamic performance, the source impedances driving vin+ and vine should be matched such that common-mode settling errors are symmetrical. these errors will be reduced by the common-mode rejection of the a/d. h h vin+ vine c pa r c pa r t t 0.5pf 0.5pf t t figure 6. switched-capacitor sha input an internal differential reference buffer creates positive and negative reference voltages, reft and refb respectively, that define the span of the a/d core. the output common mode of the reference buffer is set to midsupply, and the reft and refb voltages and span are defined as follows: reft = 1/2 ( avdd + vref ), refb = 1/2 ( avdd e vref ), span = 2 ( reft e refb ) = 2 vref it can be seen from the equations above that the reft and refb voltages are symmetrical about the midsupply voltage and, by definition, the input span is twice the value of the vref voltage. common-mode level e v 90 snr e dbc 0 85 80 75 70 65 60 55 50 0.5 1.0 1.5 2.0 2.5 3.0 e90 e85 e80 e75 e70 e65 e60 e55 e50 thd e dbc sfdr 2.5mhz 2v diff sfdr 35mhz 2v diff snr 2.5mhz 2v diff snr 35mhz 2v diff figure 7. ad92 15-105: snr, thd vs. common-mode level the internal voltage reference can be p in-strapped to fixed values of 0.5 v or 1.0 v, or adjusted within the same range as discussed in the internal reference connection section. maxi- mum snr performance will be achieved with the AD9215 set to the largest input span of 2 v p-p. the relative snr degradation will be 3 db when changing from 2 v p-p mode to 1 v p-p mode. t he sha may be driven from a source that keeps the signal peaks within the allowable range for the selected reference volt-
rev. prb AD9215 e9e preliminary technical data age. the minimum and maximum common-mode input levels are defined as follows: vcm min = vref /2 vcm max = ( avdd + vref )/2 the minimum common-mode input level allows the AD9215 to accommodate ground-referenced inputs. although optimum performance is achieved with a differential input, a single-ended source may be driven into vin+ or vine. in this configuration, one input will accept the signal, while the opposite input should be set to midscale by connecting it to an appropriate referen ce. for example, a 2 v p-p signal may be applied to vin+ while a 1 v reference is applied to vine. the AD9215 will then accept a signal varying between 2 v and 0 v. in the single-ended configuration, distortion performance may degrade significantly as compared to the differential case. however, the effect will be less noticeable at lower input frequencies. differential input configurations as previously detailed, optimum performance will be achieved while driving the AD9215 in a differential input configuration. f or baseband applications, the ad8138 differential driver provides excellent performance and a flexible interface to the a/d converter. the output common-mode voltage of the ad8138 is e asily set to avdd/2, and the driver can be configured in a sallen key filter topology to provide band limiting of the input signal. ad8138 AD9215 vin+ vine av d d a gnd 1v p-p r r c c 499 499 499 523 49.9 1k 1k 0.1 f figure 8. differential input configuration using the ad8138 at input frequencies in the second nyquist zone and above, the performance of most amplifiers will not be adequate to achieve the true performance of the AD9215. this is especia lly true in if undersampling applications where frequencies in the 70 mhz to 200 mhz range are being sampled. for these applications, d ifferential transformer coupling is the recommended input configuration, as shown in figure 9. AD9215 vin+ vine avdd a gnd 2v p-p r r c c 49.9 0.1 f figure 9. differential transformer-coupled configuration the signal characteristics must be considered when selecting a transformer. most rf transformers will saturate at frequencies below a few mhz, and excessive signal power can also cause core saturation, which leads to distortion. single-ended input configuration a single-ended input may provide adequate performa nce in cost-sensitive applications. in this configuration there will be a degr adation in sfdr and distortion performance due to the large input common-m ode swing. however, if the source imped- a nces on each input are kept matched, there should be little effect on snr p erformance. figure 10 details a typical single-ended input configuration. 2v p-p r r c c 49.9 0.1 f 10 f 10 f 0.1 f AD9215 vin+ vine avdd a gnd figure 10. single-ended input configuration clock input and considerations ty pical high-speed a/d converters use both clock edges to generate a variety of internal timing signals, and as a result may be sensitive to clock duty cycle. commonly a 5% tole rance is r equired on the clock duty cycle to maintain dynamic perfor- mance characteristics. the AD9215 contains a clock duty cycle s tabilizer that retimes the nonsampling edge, providing an internal clock signal with a nominal 50% duty cycle. this allows a wide range of clock input duty cycles without affecting the performance of the AD9215. as shown in tpc 20, noise and distortion performance are nearly flat over a 30% range of duty cycle. t he duty cycle stabilizer uses a delay-locked loop (dll) to create the nons ampling edge. as a result, any changes to the sampling frequency will require approximately 100 clock cycles to allow the dll to acquire and lock to the new rate. high-speed, high-resolution a/ds are sensitive to the quality of the clock input. the degradation in snr at a given full-scale input frequency (f input ) due only to aperture jitter (t a ) can be calculated with the following equation: snr degradation = 20 log 10 [1/2 f input t a ] in the equation, the rms aperture jitter, t a , represents the root- s um square of all j itter sources, which include the clock input, analog input signal, and a/d aperture jitter specification. under- sampling applications are particularly sensitive to jitter. th e clock input should be treated as an analog signal in cases where aperture jitter may affect the dynamic range of the AD9215. pow er supplies for clock drivers should be separated from the a/d output driver supplies to avoid modulating the clock signal with digital noise. low jitter, crystal-controlled oscillators make the best clock sources. if the clock is generated from another type of source (by gating, dividing, or other methods), it should be retimed by the original clock at the last step.
rev. prb AD9215 e10e preliminary technical data power dissipation and standby mode as shown in figure 11, the power dissipated by the AD9215 is pr oportional to its sample rate. the digital power dissipation d oes not vary substantially between the three speed grades, because it is determined primarily by the strength of the digital drivers and the load on each output bit. the maximum drvdd current can be calculated as: i drvdd = v drvdd c load f clock n where n is the number of output bits, 10 in the case of the AD9215. t his maximum current is for the condition of every output bit switching on every clock cycle, which can only occur for a full-scale square wave at the nyquist frequency, f clock /2. in practice, the drvdd current will be established by the average number of output bits switching, which will be determined by the encode rate and the characteristics of the analog input signal. sample rate e msps 325 0 total power e mv 300 275 250 225 200 175 150 125 100 75 10 20 30 40 50 60 0 50 AD9215e105 AD9215e80 AD9215e60 figure 11. total power vs. sample rate with f in = 10 mhz digital power consumption can be minimized by reducing the capacitive load presented to the output drivers. the data in figure 11 was taken with a tbd pf load on each output driver. the analog circuitry is optimally biased so that each speed grade provides excellent performance while affording reduced power consumption. each speed grade dissipates a baseline power at low sample rates that increases linearly with the clock frequency. by asserting the pdwn pin high, the AD9215 is placed in standby mode. in this state the a/d will typically dissipate 1 mw if the clock and analog inputs are static. during standby the output drivers are placed in a high-impedance state. reasserting the pdwn pin low returns the AD9215 into its normal opera- tional mode. low power dissipation in standby mode is achieved by shutting down the reference, reference buffer, and biasing networks. the decoupling capacitors on reft and refb are discharged when e ntering standby mode, and then must be recharged when return- in g to normal operation. as a result, the wake-up time is related to the time spent in standby mode, and shorter standby cycles wi ll result in proportionally shorter wake-up times. with the r ecommended 0.1 f and 10 f decoupling capacitors on reft and refb, it takes approximately one second to fully dis- charge the reference buffer decoupling capacitors and 5 ms to restore full operation. digital outputs the AD9215 output drivers can be configured to interface with 2.5 v or 3.3 v logic families by matching drvdd to the digital supply of the interfaced logic. the output drivers are sized to provide sufficient output current to drive a wide variety of logic fa milies. however, large drive currents tend to cause current glitches on the supplies that may affect converter performance. applications requiring the adc to drive large capacitive loads or large fan-outs may require external buffers or latches. as detailed in table iii, the data format can be selected for either offset binary or two?s complement. table i. reference sense operation external internal resulting sense op amp selected resulting differential connection configuration mode vref (v) span (v p-p) avdd n/a externally supplied reference n/a 2 external reference vref voltage follower (g = 1) internal 0.5 v reference 0.5 1.0 external divider noninverting (1 < g < 2) programmed variable reference 0.5 (1 + r2/r1) 2 vref agnd to 0.2 v internal divider internally programmed 1 v reference 1.0 2.0 table ii. AD9215 digital output coding code vin+ e vine vin+ e vine digital output digital output input span = 2vp-p input span = 1vp-p offset binary two?s complement (v) (v) (d9d0) (d9d0) 1023 1.000 0.500 11 1111 1111 01 1111 1111 512 0 0 10 0000 0000 00 0000 0000 511 e0.00195 e0.000978 01 1111 1111 11 1111 1111 0 e1.00 e0.5000 00 0000 0000 10 0000 0000
rev. prb AD9215 e11e preliminary technical data table iii. mode selection mode data duty cycle voltage format stabilizer avdd two?s complement disabled 2/3 avdd two?s complement enabled 1/3 avdd offset binary enabled agnd (default) offset binary disabled th e mode pin is internally pulled down to agnd by a 20 k resistor. timing the AD9215 provides latched data outputs with a pipeline delay of five clock cycles. data outputs are available one propagation delay (t od ) after the rising edge of the clock signal. refer to figure 1 for a detailed timing diagram. the length of the output data lines and loads placed on them should be minimized to reduce transients within the AD9215; these transients can detract from the converter?s dynamic performance. the lowest typical conversion rate of the AD9215 is 1 msps. at clock rates below 1 msps, dynamic performance may degrade. voltage reference a stable and accurate 0.5 v voltage reference is built into the AD9215. the input range can be adjusted by varying the refer- ence voltage applied to the AD9215, using either the internal reference or an externally applied reference voltage. the input span of the a/d tracks reference voltage changes linearly. internal reference connection a comparator within the AD9215 detects the potential at the s ens e pin and configures the reference into four possible states, which are summarized in table i. if sense is grounded, the reference amplifier switch is connected to the internal resis- tor divider (see figure 12), setting vref to 1 v. connecting the sense pin to the vref pin switches the amplifier output to the sense pin, configuring the internal op amp circuit as a voltage follower and providing a 0.5 v reference output. if an external resistor divider is connected as shown in figure 13, the switch will again be set to the sense pin. this will put the reference amplifier in a noninverting mode with the vref out- put defined as follows: vref r r =+ 05 1 2 1 . sense adc core select logic AD9215 vref vine vin+ refb reft 0.1 f 10 f 0.1 f 10 f 0.1 f 0.1 f 0.5v 7k 7k figure 12. internal reference configuration in all reference configurations, reft and refb drive the a/d conversion core and establish its input span. the input range of the a/d always equals twice the voltage at the reference pin for either an internal or an external reference. sense adc core select logic AD9215 vref vine vin+ refb reft 0.1 f 10 f 0.1 f 10 f 0.1 f 0.1 f 0.5v r 2 r 1 figure 13. programmable reference configuration
rev. prb AD9215 e12e preliminary technical data 0.5v error (%) 1v error (%) load e ma 0.05 0.0 error e % 0.00 e0.05 e0.10 e0.15 e0.20 e0.25 0.5 1.0 1.5 2.0 2.5 3.0 figure 15. vref accuracy vs. load operational mode selection as discussed earlier, the AD9215 can output data in either offset binary or two?s complement format. there is also a provi- sion for enabling or disabling the clock duty cycle stabilizer (dcs). the mode pin is a multilevel input that controls the data format and dcs state. the input threshold values and corresponding mode selections are outlined below. evaluation board t he AD9215 evaluation board provides all of the support cir cuitry required to operate the a/d in its various modes and con figurations. the converter can be driven differentially, through an ad8138 driver or a transformer, or single-ended. separate power pins are provided to isolate the dut from the support circuitry. each input configuration can be selected by proper connection of various jumpers (refer to the schematics). figure 16 shows the typical bench characterization setup used to evaluate the ac performance of the AD9215. it is critical that signal sources with very low phase n oise (< 1 picosecond rms jitter) be used to realize the ultimate performance of the con- verter. proper filtering of the input signal, to remove harmonics and lower the integrated noise at the input, is also necessary to achieve the specified noise performance. complete schematics and layout plots follow, which demon- strate the proper routing and grounding techniques that should be applied at the system level. external reference operation the use of an external reference may be necessary to enhance the gain accuracy of the a/d or improve thermal drift character- istics. when multiple a/ds track one another, a single reference (internal or external) may be necessary to reduce gain matching errors to an acceptable level. a high-precision external reference may also be selected to provide lower gain and offset tempera- ture drift. figure 14 shows the typical drift characteristics of the internal reference in both 1 v and 0.5 v modes. temperature e c 1.2 e40 v ref e error e % 1.0 0.8 0.6 0.4 0.2 0.0 e30 e20 e10 0 10 20 30 40 50 60 70 80 v ref = 1.0v v ref = 0.5v 80 figure 14. typical vref drift when the sense pin is tied to avdd, the internal reference will be disabled, allowing the use of an external reference. an internal reference buffer will load the external reference with an equivalent 7 k load. the internal buffer will still generate the positive and negative full-scale references, reft and refb, for the a/d core. the input span will always be twice the value of the reference voltage; therefore, the external reference must be limited to a maximum of 1 v. if the internal reference of the AD9215 is used to drive multiple converters to improve gain matching, the loading of the refer- e nce by the other converters must be considered. figure 15 depicts how the internal reference voltage is affected by loading. r and s smg, 2v p-p signal synthesizer r and s smg, 2v p-p signal synthesizer refin 10mhz refout b andpass filter 3v e+ 3v e+ 3v e+ 3v e+ av d d dut av d d gnd gnd dut drvdd dvdd xfmr input clock j1 AD9215 evaluation board data capture and processing figure 16. evaluation board connections
prb e13 c02874??/02(prb) printed in u.s.a. AD9215 outline dimensions 28-lead thin shrink small outline package [tssop] (ru-28) dimensions shown in millimeters 4.50 4.40 4.30 28 15 14 1 9.80 9.70 9.60 6.40 bsc pin 1 seating plane 0.15 0.05 0.30 0.19 0.65 bsc 1.20 max 0.20 0.09 0.70 0.60 0.50 8 0 coplanarity compliant to jedec standards mo-153ae 32-lead frame chip scale package[lfcsp] (cp-32) dimensions shown in millimeters and (inches) 1 32 8 9 25 24 16 17 bottom view 0.50 (0.0197) 0.40 (0.0157) 0.30 (0.0118) 0.30 (0.0118) 0.23 (0.0091) 0.18 (0.0071) 3.50 (0.1378) ref 0.50 (0.0197) bsc 12 max 0.20 (0.0079) ref 0.70 (0.0276) max 0.65 (0.0256) nom pin 1 indicator top view 5.00 (0.1969) bsc sq 4.75 (0.1870) bsc sq 0.90 (0.0354) max 0.85 (0.0335) nom 0.05 (0.0020) 0.01 (0.0004) sq 3.25 (0.1280) 3.10 (0.1220) 2.95 (0.1161) 0.60 (0.0236) 0.42 (0.0165) 0.24 (0.0094) 4 controlling dimensions are in millimeters; inch dimensions (in parentheses) are rounded-off millimeter equivalents for reference only and are not appropriate for use in design compliant to jedec standards m0-020 coplanarity seating plane preliminary technical data

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